Temporary storage of information for today's computing devices is provided by Random Access Memory (RAM). As computer software programs become ever larger and more complex, more and more RAM is required in order to perform the desired computations. A necessary resource, the amount of RAM available for a given task affects the processing capability of any computing system. A RAM component includes a number of cells or storage locations each of which can hold the logic state of a single binary-digit (bit), the smallest amount of information used by a computer. Each bit is either active or inactive, ‘1’ or ‘0’, respectively.
Large arrays of RAM cells are used to store vast amounts of information. In order to access individual items from these vast arrays, the RAM cells are arranged so that they can be addressed, much like small mailboxes at street intersections, into groups that are most commonly organized by Rows and Columns, each cell having a unique Row/Column reference.
As the size of RAM arrays has grown into and beyond megabits, designers of memory systems have been forced to focus much attention on considerations of size and power consumption. One approach to both of these issues has been the use of Dynamic Random Access Memory (DRAM) cells. As described first by Robert H. Dennard of IBM in U.S. Pat. No. 3,387,286 for “Field-Effect Transistor Memory,” each DRAM cell can be constructed from a single transistor and a capacitor, a design which has come to be referred to as a 1T-1C (One-transistor, One-capacitor) memory cell. In operation the transistor serves as an input to control the charging of the capacitor during writing and the interrogation of the charge on the capacitor during reading in order to determine the stored logic state. Since this configuration has no inherent remanence, as there had been with the earlier magnetic core memories or with data bit latches, leakage currents allow charge to drain from the capacitor over time, resulting in a potential loss of the associated information. It is necessary to recharge the capacitor to refresh the state of the memory cell in order to avoid loss of the information stored by it. Furthermore, when a conventional capacitor is used in the initial 1T-1C design the read out is destructive. This has been overcome with designs that use two transistors per cell to provide a nondestructive read out.
As higher density has been required of DRAM cells it has been difficult for memory designers to maintain the necessary storage capacitance of about 25 fF (femto-Farads) per cell. Capacitors have been fabricated using 3-D (three-dimensional) designs, including trench and stacked capacitors. The desire for higher k dielectrics (where k refers to the dielectric constant) has seen the replacement of silicon dioxide initially with silicon nitride and then other more exotic materials. The area required for a memory cell is measured in terms of the minimum feature size F of a given fabrication process. When the 1T-1C cell was first developed at IBM in 1968, the feature size was F=8 μm and the cell area was 20 F2. Advances in on-chip capacitors have reduced the memory cell to 6 F2, where F is below 100 nm.
Another approach to reducing the area dedicated to capacitance has been the extreme of removing the capacitor from the 1T-1C (One-transistor, One-capacitor) cell to create a 1T-0C, or Zero-capacitor, DRAM cell. First described in “A Capacitor-Less 1T-DRAM Cell” by S. Okhonin, et al. (IEEE Electron Device Letters, Vol. 23, No. 2, February 2002), this capacitor-less structure achieved the smallest area of any memory structure recognized at the time of its introduction and has become known as a floating body memory, since the necessary charge storage was accommodated by the Floating Body (FB) effect available in SOI (Silicon-on-Insulator) transistors.
The simplicity of the DRAM cell is offset by the complexity of the means for accessing and refreshing the cell. Access may require a delay of multiple clock cycles of the processor while a selected row and column are prepared before a specific cell can be written or read, and all accesses will occasionally be held off while a block of DRAM cells is refreshed. Also, with ever higher densities, the storage capacitors on which the data is stored have become so small that they can be disturbed by ionizing radiation events resulting in soft errors. Non-volatile memories that do not lose their stored information when power is lost and do not need to be periodically refreshed are highly desirable. Flash memories achieve these goals while also providing high density. However, flash memories have very slow write times, high voltage and power requirements, and reliability concerns.
A key concern in memory components is being able to generate smaller devices that consume less power. Although significant progress has been made in this area, a common problem with transistors is the gate voltage control of the channel as the device decreases in size. Gate voltage control is achieved by exerting a field effect on the channel. As the transistor size decreases, short-channel effects become more problematic and interfere with the gate voltage's ability to provide exclusive channel control. Ideally, total control of the channel should rest with the gate voltage.
The art would be advanced by providing memory cells with improved density, superior gate control, and non-volatile storage. Such devices are disclosed and claimed herein.